Archive — history, not state. Kept for its reasoning and its evidence; its plan is closed.

Compiler-speed trendline — night of 2026-08-04 → 05

All numbers are pulled from the night’s section reports (each states its own methodology); nothing here was re-measured. The machine carried 3–7 concurrent agents all night, so wall-clock numbers are comparable only within a report’s own paired A/B runs — never across reports. Paired deltas and counter-based numbers are load-immune and are what this trendline is built on.

The compiler itself (paired A/B, load-immune)

leverbeforeafterΔreport
Image-pin lock (press sys time)135.24 s31.18 s−77%seed-speed.md
Image-pin lock (press wall)330.5 s224.3 s−32%seed-speed.md
Image-pin lock (cold make seed)607.8 s386.4 s−36.4%seed-speed.md
Warm press after reseed (identity slice)289.3 s32.0 s9.0×seed-speed.md
Closure walk, 213 test closures (memo)324.8 s24.3 s13.4×battery-speed.md
Warm ./pit test wall (memo)62.3 s54.1 s−13%battery-speed.md
Fuzz wall (join arm 1-in-4 sampling)24.7 s17.4 s−29%battery-speed.md
Fleet width (peak jobs, 15 cores)7715RSS sanity, no throughput costseed-speed.md
Native call overhead (P8 streamline)32.6–34.4 ns28.6–30.7 ns−11–12%p8-native.md

Earlier in the day (pre-night, for the fuller arc): inline parent-map cache took streamline on the corpus 15.3 s → 7.1 s; linked-dep stat short-circuit took hot ps 0.4 s → ~0.03 s.

Where the remaining compile time is (post-fixes attribution)

  • Streamline is 90–98% of a unit compile; initial_optimize_and_lower 34.3% and range_reconciliation 22.4% are the top phases (seed-speed.md §3). range_reconciliation is the next single target.
  • make seed still runs three presses of the same 149 derivations into three empty shops — 86% of seed wall. Sharing needs a design ruling (fixpoint-independence) — queued as a morning decision.
  • shop_fetch requirements_result walks serially (~40 s/seed) — proposal stands, now safe to build against the staleness contract.
  • Uncontended compile throughput measured at 536–617 lines/s; the 69k-line seed is ~120 core-seconds of honest work. Post pin-lock, the top press profile leaf is the interpreter itself — the lock storm is gone.

Program output (the other prong, same night)

levermeasurereport
Link (P6 semantic, now the SHIP PRESS PATH)−5.88% artifact bytes, literal rows −58.6%, −1.54% instructions, 1.65× compile once per closure — the only lever that clears the ruled 5%-for-2× barswitch-report.md
Cross-unit inlining (CP2 ph3)−8.1% linked instructions on the seam corpus; guards unchanged; blocked from real modules by the export recognizerlink-opt.md
Join lattice at link−4.71% guards for 4.39× linked-streamline wall → default OFF (integrator flip, morning ruling)link-opt.md
type_checks pass (existing)+23.3% instructions if disabled — and compile gets SLOWER without itswitch-report.md
panic_outline (existing)+10.7% instructions if disabledswitch-report.md
Boot cart at the press switch−45,158 B across 68 sections; +292,352 B from the linker itself entering the shop closure (net +250 KB — morning decision)press-switch.md
Non-shop cement (logger)−4,096 B, guards 9,627 → 9,459press-switch.md

Source: plans/archive/night-2026-08-04/benchmarks.md